A logic circuit cannot operate at the specified speed unless signal delay time is within a target cycle time for all signal paths from flip-flop to flip-flop (or equivalent element). Therefore, after doing logic design, delay analysis must be performed at the stage of packaging design (placement of logic components and design of their interconnection routing) to verify whether the circuit operates correctly. That is, the packaging design is done so that all signal paths come within the target cycle time.
Signal path delay time is the sum of the delay time within each component and the delay time due to interconnection between components. The delay time within each component is stored in a library as component design data. As LSI speed increases, the proportion of the delay due to interconnection between LSI devices can become substantial, and the length of interconnection can vary greatly depending on the component placement. This increases the importance of the delay analysis at the packaging design stage.
In some cases, the delay analysis is carried out tentatively at a stage before working on routing design, in order to optimize the component placement as much as possible, and in other cases, it is carried out after completing the interconnection routing. Further, the component placement and routing in the packaging design process may be carried out wholly by a designer, or may be carried out first using an automatic process by CAD and then corrected by a designer to complete the design.
However, the prior art delay analysis process in packaging design using CAD involves the following problems. The designer iteratively performs operations which involve moving components, checking values after placement, and determining the placement if problems are solved or moving the components again if they are not solved. The prior art process involving moving and rearranging the components, therefore, takes time in processing. The processing time is further lengthened by subsequent recalculations of delay values for all signal paths. Since the designer moves the components by making guesses, it is not uncommon that an error path occurs again, and thus the time required for iterative processing becomes considerable. Here, one problem is that the results of checking are not known until after rearranging the components. Another problem is that the side effect resulting from moving the components, that is, the increase in the delay time in other signal paths, is also not known.
Furthermore, in determining the optimum placement of the components, not only the signal path delay time described above but the ease of interconnection routing must also be considered.